Job Details

Principal Solutions Engineer page is loaded## Principal Solutions Engineerlocations: SAN JOSEtime type: Full timeposted on: Posted Todayjob requisition id: R51364## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.****Job Duties:*** Research, design, develop, and test electronic components and systems for Electronic Design Automation (EDA) and semiconductor intellectual property (IP) employing knowledge of electronic theory and materials properties.* Implement the netlist through 3DIC flow and showcase design convergence.* Work on chiplet Signal Integrity (SI) and Power Integrity (PI) analysis and provide engineering and design fixes to meet specifications.* Develop timing analysis flow and methodology for 3DIC, scalable to support heterogenous chiplets.* Responsible for 3DIC flow setup to achieve best chiplet partitioning for optimal chip to chip communication.* Analyze different chiplet floorplan for minimal distance/connection between chiplets.* May telecommute.* Must be available to work on projects at various, unanticipated sites throughout the United States.**Qualifications:*** Master's degree in Electrical Engineering, Electronic Engineering, or related field* Minimum five (5) years of experience in the job offered or in a related occupation.* Synthesis, Place and Route (P&R), and design closure techniques to demonstrate best Power-Performance-Area (PPA) optimization* Develop tools and methodologies for handling advance process node needs, such as sub 4nm across different foundries using ASIC design knowledge* Utilize EDA's best available solution in the IC digital implementation and signoff space to drive solutions that address new problems and improve productivity* High performance core closure using Cadence synthesis and place and route solutions to performance power vs. power vs. area trade-off* Signoff domain, including extraction, timing, and EMIR to drive full flow (rtl2gds)* Advance package design and IC-package co-optimization* Chiplet design, system planning, and analysis* Must be available to work on projects at various, unanticipated sites throughout the United States.The annual salary range for California is $216,091 to $228,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the base salary range is a guideline, and individual total compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs includes: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.## **We're doing work that matters. Help us solve what others can't.**Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.#J-18808-Ljbffr